1. Field of the Invention
The present invention relates to electronic packages, and more particularly, to an electronic package and a fabrication method thereof for improving the product reliability.
2. Description of Related Art
Along with the progress of electronic industries, electronic products are developed toward the trend of miniaturization and multi-function. Accordingly, various package types have been developed. To meet the demands of semiconductor devices for high integration, miniaturization and high electrical performance, wafer level chip scale packaging (WLCSP) technologies have been developed.
FIGS. 1A to 1E are schematic cross-sectional views showing a method for fabricating a WLCSP package 1 according to the prior art.
Referring to FIGS. 1A and 1B, a wafer 12′ is cut into a plurality of semiconductor elements 12 and then the semiconductor elements 12 are disposed on an adhesive layer 11 of a carrier 10. Thereafter, the semiconductor elements 12 are tested. Each of the semiconductor elements 12 has an active surface 12a with a plurality of electrode pads 120, an inactive surface 12b opposite to the active surface 12a, and a side surface 12c adjacent to and connecting the active and inactive surfaces 12a, 12b. The semiconductor element 12 is disposed on the adhesive layer 11 via the active surface 12a thereof.
Referring to FIG. 1C, an encapsulant 13 is formed on the adhesive layer 11 to encapsulate the semiconductor elements 12.
Referring to FIG. 1D, the carrier 10 and the adhesive layer 11 are removed to expose the active surfaces 12a of the semiconductor elements 12.
Referring to FIG. 1E, an RDL (redistribution layer) process is performed to form an RDL structure 14 on the encapsulant 13 and the active surfaces 12a of the semiconductor elements 12. The RDL structure 14 is electrically connected to the electrode pads 120 of the semiconductor elements 12.
Then, an insulating layer 15 is formed on the RDL structure 14. Portions of the RDL structure 14 are exposed from the insulating layer 15 and a plurality of conductive elements 16 such as solder bumps are mounted on the exposed portions of the RDL structure 14.
Thereafter, a singulation process is performed along a cutting path S of FIG. 1E to form a plurality of packages 1.
However, since the active surfaces 12a of the semiconductor elements 12 have a quite low structural strength, cracking easily occurs to the semiconductor elements 12 during the processes of FIGS. 1A and 1B and consequently the conductive elements 16 easily delaminate from the semiconductor elements 12. Further, such a cracking cannot be detected since a test process is generally performed before separation of the semiconductor elements 12. As such, when the package 1 is picked up and placed at a suitable position and subjected to an SMT (surface mount technology) process, the above-described drawbacks easily result in a reduced product yield.
Therefore, how to overcome the above-described drawbacks has become critical.